library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity max2clk_24 is
port(
      clk: in std_ulogic;
		  x1,x2: in std_ulogic_vector(23 downto 0);
		  y:out std_ulogic_vector(23 downto 0)
	);
end max2clk_24;

architecture beh of max2clk_24 is


begin
process(clk)
  begin
    if clk'event and clk='1' then
      if x1(23)='0' and x2(23)='0'  then
	      if x1<x2 then
	        y<=x2;
	      else 
	        y<=x1;
	      end if;
      elsif x1(23)='1' and x2(23)='1'  then
        if x1<x2 then
           y<=x2;
        else
           y<=x1;
        end if;
      elsif x1(23)='0' and x2(23)='1'  then
          y<=x1;
      else
          y<=x2;
      end if;
    end if;
end process;

end beh;
